Ex parte KAHLE et al. - Page 8

        Appeal No. 96-1426                                                              
        Application 08/001,863                                                          

        special ALU.  Therefore, it is difficult to see the relevance of                
             As to the limitation of "dispatching each scalar instruction               
        . . . which includes no more than N source operands upon                        
        elimination of possible data dependency hazards, as indicated by                
        said source-to-destination dependency interlock circuitry," the                 
        examiner finds (Examiner's Answer, pages 2-3):                                  
                  a)each scalar instruction [NR R1,R2] or [AR R3,R4]                    
             (e.g. see col.9, lines 65-68; col.10, lines 2-5) which                     
             includes no more than N (e.g. (R1,R2) or (R3,R4); N =2)                    
             source  operands  upon  eliminating  (e.g.  see  col.9,                    
             lines 45-56) passible [sic, possible] data hazards by a                    
             dependency interlock circuit [ALU] (e.g. see col.10,                       
             lines 12-68; col.11, lines 1-16; see also col.2, lines 58-68               
             for the relief of data dependency interlocks); . . . .                     
        The logical and arithmetic instructions have only one source                    
        operand, the other operand is the destination operand, so N=1,                  
        not N=2 as found by the examiner.  The data dependency collapsing               
        ALU in Vassiliadis is not "source-to-destination dependency                     
        interlock circuitry" because it does not interlock instructions:                
        it eliminates interlocks between instructions using a special                   
        ALU.  However, Vassiliadis discloses in the background that the                 
        detection and resolution of structural and data dependency                      
        hazards may be implemented in hardware (column 1, lines 51-55).                 
        This presumably is the same hardware as the "data dependency                    
        interlock circuits" in the prior art described by appellants                    

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