Appeal No. 96-1426
Application 08/001,863
dependency interlock circuit (specification, page 3). Appellants' method and system eliminates
data dependency hazards where the instructions include a greater number of source operands than
may be interlocked utilizing existing data dependency interlock circuitry. If the
source-to-destination dependency interlock circuitry can interlock N source operands, an
instruction having more than N source operands is dispatched only upon elimination of N possible
data dependency hazards by the source-to-destination dependency interlock circuitry and a
determination that all instructions preceding the remaining source operands have completed.
Claim 1 is reproduced below.
1. A method for increased efficiency in instruction synchronization in a superscalar
processor system capable of simultaneously dispatching multiple scalar instructions having
multiple source and destination operands and having source-to-destination dependency
interlock circuitry capable of interlocking N source operands and M destination operands
to prevent data dependency hazards, said method comprising the steps of:
dispatching each scalar instruction within said superscalar processor system
which includes no more than N source operands upon elimination of possible data
dependency hazards, as indicated by said source-to-destination dependency interlock
circuitry; and
dispatching each scalar instruction which includes more than N source
operands only upon elimination of possible data dependency hazards for a first N source
operands, as indicated by said source-to-destination dependency interlock circuitry and a
completion of all preceding instructions, wherein possible data dependencies for scalar
instructions which include N+1 or more source operands are avoided without requiring
additional dependency interlock circuitry.
The examiner relies on the following reference:
Vassiliadis et al. (Vassiliadis) 5,051,940 Sep. 24, 1991
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