Appeal No. 96-1426
Application 08/001,863
examiner's reliance on the address hazard-collapsing ALU in
Vassiliadis as teaching N+1 operands is misplaced. It is true
that the address instructions are shown with two source operands
instead of one for the logical and arithmetic instructions.
However, Vassiliadis handles sequences with address instructions
having two source operands in the same manner as logical and
arithmetic instructions having one operand: collapsing the data
dependencies using a special ALU, in this case one with four
inputs. Nothing in Vassiliadis suggests eliminating some data
dependencies for operands with interlock hardware and then
awaiting execution of all previous instructions prior to the
remaining instruction operands.
It is admitted that "[o]ne technique for ensuring that such
so-called 'data dependency hazards' do not occur is the
restriction of the dispatching of a particular instruction until
such time as all preceding instructions have been dispatched"
(specification, page 3). It is stated that "the method and
system of the present invention processes three source operand
instructions by delaying dispatch of such instructions until all
preceding instructions have completed, eliminating possible data
dependency hazards" (specification, page 10). Thus, the
condition of delaying dispatch until all preceding instructions
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