Appeal No. 96-1426
Application 08/001,863
Consider the sequence of instructions, where NR and AR are opcodes and R1-R4 are
registers (note that these instructions have the form: "Opcode (Destination), (Source)")
(column 9, line 68 to column 10, line 1):
NR R1, R2
AR R3, R4
Data dependency interlocks occur with register combinations 7-12 listed at the top of column 11,
e.g., "R1=R3+ R2+ R4" (i.e., destination operand R1 must be written by
instruction NR before it is written by instruction AR) or
"R1=R4+ R2+ R3" (i.e., destination operand R1 must be written by
instruction NR before it is read as a source operand by
instruction AR). Vassiliadis considers two types of
instructions: logical (LOGICAL) and arithmetic (ADD). The four
sequences of the two types of operations (LOGICAL/LOGICAL,
LOGICAL/ADD, ADD/ADD, ADD/LOGICAL) give rise to data dependency
interlocks for each of the five interlock conditions, for a total
of 20 instruction combinations with interlocking. Figure 5
specifies the operations that must be performed on the operands
to collapse the interlocks. Figures 6A and 6B specify the ALU
operations required to be performed on operand inputs AI0, AI1,
and AI2. Figures 7A and 7B specify the routing of the operands
for the ALU to perform the operations of figure 5. Figure 9
shows a logical representation of the data dependency collapsing
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Last modified: November 3, 2007