Appeal No. 96-1014
Application 08/032,530
of processing would necessarily operate by inhibiting and
then permitting fetching and executing using a program
counter (EA4). Appellant does not appear to contest this
reasoning. We agree that stored program computers use
program counters to store the address of the next
instruction to be executed. Although some evidence from the
examiner would have been preferable, in our opinion, one of
ordinary skill in the art of synchronizing processors would
have known that one way to interrupt and continue the
processing in Kametani would have been to inhibit the
fetching of the instruction in the program counter and then
permit fetching and executing of the next instruction in the
program counter. This reasoning is based on obviousness,
not inherency.
For these reasons, we sustain the rejection of
claims 23 and 35, and also dependent claims 24, 25, and
36-38, which have been grouped to stand or fall with claims
23 and 35.
Claims 26-34 and 39-44
Claim 30 recite a "synchronization flag memory having
stored therein an indication of whether said processor is in
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