Appeal No. 96-1014
Application 08/032,530
a synchronized mode or in an unsynchronized mode" which is
connected to the synchronization logic unit, and the
synchronization logic unit permits "the fetching of the next
instruction by said program counter register regardless of
the status of said synchronization bus and said
synchronization register when said synchronization memory
flag indicates said unsynchronized mode." Claim 26 contains
similar limitations. Process claim 39 recites "storing at
each processor an indication of a synchronized mode or an
unsynchronized mode" and "permitting fetching an instruction
at each processor regardless of the status of the ready
signal of the other processors when said processor stores an
indication of the unsynchronized mode." Appellant argues
that this "permits changing a processor between synchronized
and unsynchronized modes without changing the indication of
which processors that the processor is to be synchronized
[with] stored in synchronization register 2207" (Br7).
The examiner states (EA9):
Jaswa on column 2 line 17 shows setting a synch flag
when synchronized operations are to be performed.
Please note that this flag is set only when
synchronization mode is selected, as mentioned above.
Also, on column 1, lines 34-53 Jaswa states that it is
desirable to run the processors asynchronously between
- 11 -
Page: Previous 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Next
Last modified: November 3, 2007