Appeal No. 96-1014
Application 08/032,530
modify Kametani to arrive at the claimed synchronization
flag memory.
Appellant correctly notes that "[i]n Kametani a
processor may be placed in a mode not synchronized with any
other processor by writing all zeros into synchronous
register 5 of Figure 1" (Br8). Appellant argues that "[t]he
synchronization flag memory recited in claim 30 is clearly a
different structure than the synchronization register"
(Br9). We agree. The processors in Kametani can be run
unsynchronized, but this does not meet the synchronization
flag memory limitation.
Appellant argues that the examiner failed to point out
a flag memory or software setting of the flags in Kametani
or Jaswa in the Final Rejection or the Examiner's Answer
(e.g., Br9, RBr10). The examiner responds (SEA6): "It is
submitted that the appellant argues details which are not
critical such as whether there is a memory to store a flag
and/or whether an instruction sets the flag or the hardware
sets the flag and obscure the invention which is selective
synchronization of the processors using the registers as
shown in Kametani." We agree with appellant's response
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