Appeal No. 96-1014
Application 08/032,530
the final rejection of claims 23-44, which constitute all of
the pending claims.
We affirm-in-part.
BACKGROUND
The disclosed invention is directed to an apparatus and
method for operating a plurality of processors in
synchronism, as described with respect to figures 21-23 in
the section of the specification at pages 38-44 entitled
"Synchronized MIMD."
Claim 35 is reproduced below.
35. The method of operating a computer system
having a plurality of processors in synchronism, each
of the processors independently fetching and executing
instructions, said method comprising the steps of:
storing at each processor an indication of other
processor or processors to which said processor is to
be synchronized;
generating at each processor a ready signal when
said processor is ready to fetch an instruction;
inhibiting fetching an instruction at each
processor until said processor receives said ready
signal from all other processor or processors to which
said processor is to be synchronized according to said
stored indication and thereafter fetching said
instruction at each processor; and
executing fetched instructions at each processor,
whereby each processor is synchronized with said other
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