Appeal No. 96-1014
Application 08/032,530
In re Jacoby, 309 F.2d 513, 516, 135 USPQ 317, 319 (CCPA
1962); In re Oetiker, 977 F.2d 1443, 1447-48,
24 USPQ2d 1443, 1446-47 (Fed. Cir. 1992) (Nies, C.J.,
concurring). We find that the level of ordinary skill in
the pertinent art of designing synchronized processors is
very high and involves extensive knowledge of computer
architecture, logic design, and software.
Claims 23-25 and 35-38
Kametani discloses an apparatus for synchronizing
processors which is markedly similar to appellant's
apparatus in figure 22. Kametani has a signal line 8
corresponding exactly to appellant's synchronization bus 40;
a synchronous register 5 corresponding exactly to
appellant's sync register 2207; and a monitoring circuit 6
(shown in more detail in figure 2) corresponding exactly to
appellant's synchronization logic gates 2202-2206. The
trigger signal 10 in Kametani corresponds to appellant's
E'E'C'U'T'E' signal. In Kametani, the pulse on signal line 4'X
from the processor to the flip-flop 7 and the resulting "0"
on the terminal Q of the flip-flop 7 correspond to
appellant's claimed "okay to synchronize" signal. Kametani
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