Appeal No. 96-1014
Application 08/032,530
differs from the disclosed structure from appellant's
figure 22 in its use of a flip-flop 7 to generate the "okay
to synchronize" signal instead of a NAND gate 2201. It is
true, as noted by appellant (RBr3-4), there are differences
in the way the Kametani's circuitry works because of the
flip-flop; however, the issue is whether any claimed
differences would have been obvious.
Appellant argues (Br5), with respect to claims 23 and
35, that the combination of Kametani and Jaswa fails to
teach or suggest: (1) synchronization "on an instruction by
instruction basis"; and (2) inhibiting the fetching of
instructions until each processor has transmitted a signal
that the processor is ready to synchronize and then fetching
and executing an instruction, which is carried out with a
"program counter register" in apparatus claim 23.
As to synchronization "on an instruction by instruction
basis," appellant argues (Br6): "First, Kametani fails to
disclose instruction by instruction synchronization and
specifically teaches task synchronization that may take
differing times. Second, Jaswa mentions instruction by
instruction synchronization, but states that this is
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