Appeal No. 1997-2041
Application No. 08/337,131
Claim 1 is illustrative of the claimed invention, and
reads as follows:
1. A method of forming an array of electrically erasable non-
volatile memory devices on a semiconductor substrate including
a monocrystalline silicon layer comprising the steps of:
doping spaced-apart first regions with dopant of a type
opposite that of the monocrystalline silicon layer to form a
plurality of source areas and a plurality of drain areas, said
source areas and said drain areas spaced apart;
growing field oxide areas over the first regions;
growing a tunnel oxide layer between the field oxide
areas, the tunnel oxide lying over a plurality of second
regions, the second regions lying between the first regions;
forming a plurality of floating gate members, wherein at
least a portion of the floating gate members is formed
subsequent to the formation of the plurality of source areas
and the plurality of drain areas, wherein the portion of the
floating gate members formed subsequent to the formation of
the plurality of source areas and the plurality of drain areas
overlaps a portion of the source areas and a portion of the
drain areas thereby forming a floating gate-to-source overlap
and a floating gate-to-drain overlap, respectively, wherein
the floating gate-to-source overlap is less than the floating
gate-to-drain overlap for the portion as formed;
forming an insulating layer over the floating gate
members; and
forming a patterned control gate layer.
References1
1Our understanding of the Japanese documents is derived from a reading
of the translations prepared for the Patent and Trademark Office. Copies of
the translations are attached.
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