Ex Parte NAKAMURA et al - Page 8



          Appeal No. 2000-0660                                                        
          Application No. 08/985,278                                                  

          American Hoist & Derrick Co., 730 F.2d 1452, 1458, 221 USPQ 481,            
          485 (Fed. Cir. 1984).                                                       
               Appellants' claim 5 recites the following:                             
               wherein said insulation film comprising a nitride film                 
               and top oxide film on said nitride film, the thickness                 
               of said top oxide film being set to a thickness so that                
               the amount of transition of the carriers passing                       
               through the top oxide film is almost equal to or larger                
               than the amount of transition of the carriers passing                  
               through the tunnel film under a read voltage applied to                
               said gate electrode.                                                   
               Appellants argues that "Hayabuchi teaches a tunnel film (3)            
          that is 2 nm thick (col. 3, lines 55-56) and a top oxide layer              
          (5) which is 4 nm thick (col. 3, lines 67-68).  Consequently, the           
          4 nm top oxide layer taught by Hayabuchi cannot pass charge                 
          carriers in equal or greater quantity than the thinner 2 nm                 
          tunnel film as recited in claim 5."  See page 8, lines 25-30 of             
          the reply brief.                                                            
               On page 4, lines 1-4 of the answer, the Examiner argues that           
          Hayabuchi discloses the nonvolatile semiconductor memory with               
               a tunnel film (3) having a thickness of approximately 2                
               nm formed on the channel forming region; an insulating                 
               film formed on the tunnel film, the insulating film                    
               including a silicon nitride layer (4) and a top oxide                  
               layer (5) with a thickness approximately 1 nm; [and] a                 
               gate electrode (9) formed on the insulating film.                      



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