Ex Parte KODAMA - Page 2




          Appeal No. 2001-2659                                                        
          Application 08/919,674                                                      


          Claim 1 is illustrative:                                                    
               1.   A method for manufacturing a nonvolatile semiconductor            
          storage device comprising the steps of:                                     
               forming an element separating oxide layer onto a                       
          semiconductor base for defining a first region for forming a                
          nonvolatile memory cell and a second region for forming an MOS              
          transistor for use in a peripheral circuit;                                 
               forming a first gate insulating layer on said first and                
          second regions of a surface of said semiconductor base;                     
               forming a first polysilicon layer over the entire surface of           
          said semiconductor base, and then patterning said first                     
          polysilicon layer in a manner such that said first polysilicon              
          layer is left covering only said first gate insulating layer of             
          said first region;                                                          
               sequentially forming a second gate insulating layer having             
          three insulating layers and a second polysilicon layer over the             
          entire surface of said first region and said second region;                 
               sequentially removing said second polysilicon layer, said              
          second gate insulating layer and said first gate insulating                 
          layer, respectively, in said second region;                                 
               forming a third gate oxide layer over a surface of said                
          semiconductor base corresponding to said second region by means             
          of thermal oxidation;                                                       
               coating a third polysilicon layer over the entire surface of           
          said first region and said second region, and patterning said               
          third polysilicon layer to form a gate electrode over said second           
          region; and                                                                 
               patterning said second polysilicon layer, said second gate             
          insulating layer, and said first polysilicon layer to form a gate           
          electrode in said first region wherein a control gate is formed             
          by patterning said second polysilicon layer, said second gate               
          insulating layer and said first polysilicon layer, and a floating           
          gate is formed by patterning said first polysilicon layer.                  

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