Ex Parte KODAMA - Page 5




          Appeal No. 2001-2659                                                        
          Application 08/919,674                                                      


          layer of the first region as required by the appellant’s claims 1           
          and 2.  The first polysilicon layer in the second region is not             
          removed in this step because the first polysilicon layer is used            
          as a buffer layer for preventing the semiconductor substrate                
          surface from being contaminated or damaged when a subsequently-             
          applied interlayer insulating film (6) is etched from the second            
          region (col. 6, lines 1-5).  Kume’s first polysilicon layer is              
          not removed until after carrying out the next step in the                   
          appellant’s method, i.e., “sequentially forming a second gate               
          insulating layer having three insulating layers and a second                
          polysilicon layer over the entire surface of said first and said            
          second region”.3  Thus, Kume’s interlayer insulating film (6) and           
          second polycrystalline layer (7) are formed in the second region            
          on the first polysilicon layer (5) (figure 1B), whereas the                 
          appellant’s second gate insulating layer (8) and second                     
          polysilicon layer (9) are formed in the second region on the                
          first gate insulating layer (3) (figure 1B).                                



               3 Kume forms on the first polysilicon layer an interlayer              
          insulating film (6) and then a second polycrystalline layer (7)             
          (col. 5, lines 59-64; figure 1B), and then removes the second               
          polycrystalline layer, the interlayer insulating film and the               
          first polysilicon layer from the second region (col. 5, lines 65-           
          68; figure 1C).                                                             
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