Appeal No. 2001-2659
Application 08/919,674
area);
2) forming a first gate insulating layer (16) on the surface
of the elemental area (figure 7; col. 9, lines 61-63);
3) depositing a first polysilicon layer (17), for forming a
floating gate, over the entire surface of the silicon base
(figure 7; col. 9, line 63 - col. 10, line 4);
4) forming a second gate insulating layer (18, 19, 20)
having an ONO structure consisting of a first silicon oxide
layer (18) formed by thermal oxidation, a silicon nitride
layer (19) formed by chemical vapor deposition, and a second
silicon oxide layer (20) formed by thermal oxidation (figure 7;
col. 10, lines 7-16);
5) forming a second polysilicon layer (21) onto the second
gate insulating layer (18, 19, 20) (figure 7; col. 10, lines 17-
21);
6) selectively removing the second polysilicon layer (21) in
the peripheral circuit transistor region and in the second gate
insulating layer (18, 19, 20) by means of an etching process, and
patterning the first polysilicon layer (17) such that it is
selectively left covering only the elemental area,4 (figure 9;
4 The appellant’s claims do not require that the steps are
carried out in the recited sequence.
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