Appeal No. 2001-2659
Application 08/919,674
col. 10, lines 30-49);
7) forming a gate oxide layer (27) in the peripheral circuit
transistor region and forming a silicon oxide layer (27') onto
the second polysilicon layer (21) (figure 9; col. 10, lines 51-
58);
8) depositing a third polysilicon layer (lower layer of
tungsten polycide layer 28) onto the entire surface so as to form
a gate electrode of a peripheral transistor (figure 9; col. 10,
line 59 - col. 11, line 3);
9) patterning the third polysilicon layer (28) so as to form
a gate electrode comprising the third polysilicon layer (28) in
the peripheral circuit transistor region while using the silicon
oxide layer (27') as a protective layer for the second
polysilicon layer (21) (figure 11; col. 11, lines 3-15);5 and
10) patterning the second polysilicon layer (21), the second
gate insulating layer (18, 19, 20), and the first polysilicon
layer (17) so as to respectively form a control gate from the
second polysilicon layer (21), and a floating gate from the first
polysilicon layer (17) in the elemental area (figure 11; col. 11,
5 Thus, the appellant’s argument (reply brief, page 3) that
Kume does not pattern the third polysilicon layer while using the
silicon oxide layer (27') as a protective layer for the second
polysilicon layer is incorrect.
8
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