Ex Parte KODAMA - Page 6




          Appeal No. 2001-2659                                                        
          Application 08/919,674                                                      


               The examiner argues that “[t]he 1st polysilicon layer is               
          removed from the 2nd region, and the 2nd polysilicon layer is               
          removed from the 2nd region (see Figs. [sic] 1C)” (answer,                  
          page 3).  The examiner, however, does not point out any                     
          disclosure in Kume wherein the first polysilicon layer is removed           
          from the second region before the intermediate insulating film              
          and second polycrystalline layer are formed in that region.                 
               The examiner, therefore, has not carried the burden of                 
          establishing a prima facie case of anticipation of the method               
          claimed in the appellant’s independent claims 1 and 2.                      
          Accordingly, we reverse the rejection of these claims and                   
          dependent claims 3-9.                                                       
                                      Claim 10                                        
               Kume discloses a method for manufacturing a nonvolatile                
          semiconductor storage device (col. 1, lines 8-9), comprising the            
          steps of:                                                                   
               1) selectively oxidizing a surface of a silicon                        
          semiconductor substrate (11) (col. 7, lines 46-48) according to             
          the LOCOS method (col. 8, lines 65-67) so as to form an element             
          separating oxide layer (14) which defines an elemental area                 
          (figure 7, memory transistor area) and a peripheral circuit                 
          transistor region (figure 7, peripheral circuit MOS transistor              
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