Appeal No. 2001-2659
Application 08/919,674
11) patterning the WSi layer (40) along with the third
polysilicon layer (28), the second polysilicon layer (21), the
second gate insulating layer (18, 19, 20) and the first
polysilicon layer (17), so as to form, in the peripheral circuit
transistor region, a gate electrode from the WSi layer (40) and
the third polysilicon layer (28), and to form, in the memory
array region, a control gate from the WSi layer (40) and the
second polysilicon layer (21), and a floating gate from the first
polysilicon layer (17) (figure 13; col. 12, lines 13-27).
As discussed above regarding claim 10, Kume does not
disclose forming the oxide layers (18 and 20) of the second gate
insulating layer (18, 19, 20) by chemical vapor deposition as
required by claim 12.6 Accordingly, we reverse the rejection of
this claim and claim 13 which depends therefrom.
REMAND
We remand the application to the examiner for the examiner
to reopen prosecution and for the examiner and the appellant to
address on the record whether Kume, alone or in combination with
additional prior art, would have fairly suggested, to one of
ordinary skill in the art, the above-discussed requirements of
6 This is the only difference between the method claimed in
the appellant’s claim 12 and Kume’s method.
10
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