Appeal No. 2001-2659
Application 08/919,674
above-recited step must be carried out sequentially since this is
a single step.
Kume forms a first polysilicon layer (5) over the entire
surface of a semiconductor base, and then patterns the first
polysilicon layer such that it covers a gate insulating layer (3)
of both first and second regions (i.e., the first area and second
area in figure 1A) (col. 5, lines 45-53).1,2 Thus, in this step
Kume does not pattern the first polysilicon layer in a manner
such that it is left covering only the first gate insulating
1 The appellant’s argument (brief, pages 10-11) that Kume’s
gate oxide layer (3) is not a gate insulating layer is without
merit. As was well known in the semiconductor art, a gate oxide
layer is a gate insulating layer. See, e.g., S.M. Sze, Physics
of Semiconductor Devices 453 (John Wiley & Sons, 2nd ed. 1981);
Sumner N. Levine, Principles of Solid-State Microelectronics 178
(Holt, Rinehart & Winston, 1963). A copy of the relevant page of
each of these references is provided to the appellant with this
decision.
2 The appellant argues that Kume’s gate oxide layer 3 is not
equivalent to the appellant’s first gate insulating layer (3)
because the appellant’s first gate insulating layer is at least
partially removed (figure 1C) whereas Kume’s gate oxide layer 3
is not disclosed as being removed but, rather, is heated to form
gate oxide film 8 (reply brief, page 2). This argument is not
well taken because the presence of Kume’s gate oxide layer 3 in
the second area in figure 1C, and the absence of that gate oxide
layer from the second area in figure 1D, indicates that in the
etching disclosed by Kume (col. 6, lines 17-24), gate oxide
layer 3 is removed. Kume teaches that gate oxide layer 8
subsequently is formed by thermal oxidation (col. 6, lines 25-
29).
4
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