Ex Parte 4918645 et al - Page 3




         Appeal No. 2006-2217                                                       
         Reexamination Control Nos. 90/006,789 and 90/007,420                       

         a memory page boundary.  Method claims 12, 13, and 17 generally            
         correspond to apparatus claims 1, 2, and 6, respectively.                  
              Claim 1 is reproduced below.                                          
              1. Memory control apparatus for use in a data processing              
              system having at least a requesting agent and said [sic]              
              replying agent electrically coupled together by a system              
              bus, the requesting agent requesting access to a memory on            
              the replying agent for storing and retrieving data therein            
              over the system bus, the apparatus comprising:                        
                   means, associated with a replying agent, for detecting           
                 a request for initiating an access to a memory on the              
                 replying agent, the request detecting means being coupled          
                 to a system bus, and request being made over the system            
                 bus by a requesting agent;                                         
                   means, responsive to the request detecting means                 
                 detecting the request, for asserting a plurality of                
                 memory address control signals for accessing a plurality           
                 of times the memory on the replying agent, the control             
                 signals comprising at least a row address strobe signal            
                 associated with a memory row address and a column address          
                 strobe signal associated with a memory column address;             
                 and                                                                
                   means for detecting a completion of the access to the            
                 memory, the completion detecting means being responsive            
                 to an end of access control signal generated by the                
                 requesting agent, the access completion detecting means            
                 being coupled to the memory address control signal                 
                 asserting means for halting the operation thereof after            
                 the end of access control signal is detected; and wherein          
                   the memory address control signal asserting means                
              asserts the memory address control signals by asserting the           
              row address strobe in conjunction with a row address being            
              indicative of a page of data within the memory, and                   
              thereafter asserts and deasserts a plurality of times the             
              column address strobe signal in conjunction with a plurality          
              of column addresses for performing a page mode type of                
              memory access.                                                        

                                   THE REFERENCES                                   
              The examiner relies on the following references:                      

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