Appeal No. 2006-2217 Reexamination Control Nos. 90/006,789 and 90/007,420 going to the question of motivation. The memory board in Figure 2-1 of "iSBC MEM/3XX" shows that the data lines go to and from the "Cache Subsystem" and the "DRAM Subsystem." However, memory accesses are to the "cache" memory and not to the DRAM array directly. When data is not found in a line of the cache, it is retrieved from the DRAM array and put in the cache. The cache array and DRAM array both have 32-bit data fields (Figure 8-1, p. 8-2), so it is not apparent that any more than one memory transfer would be performed at a time from the DRAM array to the cache to make a page mode worthwhile. We tend to agree with the statement in the Hoffman declaration that "a person of skill in the art would have also realized that choice by the memory board manufacturer of using a cache implied that adding faster DRAM or page mode DRAM would have had little or no effect on performance" (Br43), which tends to show no motivation. The complexity of adding a page mode without interfering with the cache system is a consideration. The interconnections between the cache memory system and the DRAM memory system makes it difficult to explain what modifications would have to be made to a page mode of access. Furthermore, it is not clear, even if the memory controller was modified to allow it to perform a page mode of access to the DRAM, that the memory controller would perform a page mode of access in response to detection of a request from a requesting agent since memory requests go first to the cache. These considerations are not addressed in the rejection. While it may have been obvious to eliminate the cache memory and access the DRAM memory directly, i.e., to use a less complex system, this modification is not presented. For these reasons, the rejection does establish a prima facie case of obviousness. The rejection of claim 1 is reversed. Apparatus claim 6 contains common limitations with claim 1 and the rejection of claim 6 is also reversed. Method claims 12 and 17 have limitations corresponding to claim 1 and, therefore, the rejection of claims 12 and 17 is reversed. NEW GROUND OF REJECTION UNDER 37 CFR § 41.50(b) The following references are applied in new grounds of rejection: Bruce 4,546,451 October 8, 1985 82C08 CHMOS Dynamic RAM Controller, Intel Corp., pages 3-1 through 3-33, June 1985 ("82C08"). Multibus® II Bus Architecture Specification Handbook, Intel Corp., 1985 ("Multibus II"). - 12 -Page: Previous 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 NextLast modified: November 3, 2007