Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
controllers for page mode DRAMs (e.g., Fig. 3), we also find that
Bruce is within the inventor's field of endeavor.
Content
Multibus II
Architecture
"The Multibus II bus architecture consists of the Parallel
System (iPSB) Bus, the Local Bus Extension (iLBX II Bus), the
Serial System (iSSB) Bus, and two busses carried over from the
Multibus I architecture -- the iSBX I/O Expansion Bus and the
Multichannel DMA (Direct Memory Access) I/O Bus (Figure 1-1)"
(sheet 1-1). The Multibus II specification defines the iPSB,
iLBX, and iSSB bus structures (sheet 1-1). The busses can be
used in different combinations depending on the requirements,
including a basic system with the iPSB alone (Figure 1-2,
sheets 1-9; and Figure 1-2, sheet 2-6), which is relied on here.
The iPSB Parallel System bus has a "burst" transfer mode that
maximizes the bus bandwidth (sheet 1-4): "The burst is
implemented as a single address cycle followed by multiple data
transfers which maximize the bus bandwidth."
"Multibus II" defines the following terms, which will be
helpful in the discussion and rejection (sheets 2-2 to 2-4):
Agent A physical unit which has an interface
to the Parallel Systems bus. For
example, a single-board computer.
Transfer Cycle A bus cycle in which a bus owner
transfers data on the Parallel System
bus. The transfer cycle is subdivided
in two phases, the request phase and
the reply phase.
Request Phase The initial phase of a transfer request
in which the bus owner requests a data
transfer operation. The bus owner
places command and address information
on the Parallel System bus.
Reply Phase The final phase of a transfer cycle.
The phase consists of one or more
consecutive data and/or status
transfers on the Parallel System bus.
Requesting Agent The agent that initiates the
arbitration cycle and transfer cycles.
The requesting agent places a request
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