Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
Ripplemode is a page mode type of memory access where the row
address strobe is asserted for the entire block transfer and the
column address strobe is activated alternately.
The 82C08 automatically detects an SBE transfer by sensing
the 186/188 status lines: "status lines active means SBE transfer
is requested" (page 3-15 under "Description and Features"),
whereas "status inactive indicates SBE cycle termination" (id.).
"The SBE signal will be deactivated upon detection of the status
lines inactive, or upon column address overflow." (page 3-15
under "SBE Mode Decoding").
The input address is automatically incremented during SBE
transfer (page 3-15 under "Address Counter and Address Latch"):
The main function of this block is to generate the addresses
for the DRAM's [sic, DRAMs] in SBE mode. The ROW address
(AIH0-8) is internally latched, and upon detection of SBE,
will stay latched for the entire SBE cycle. The COLUMN
address (AIL0-8) will be latched internally by the SBE
signal, into an internal counter which supplies the column
address during SBE cycle.
The timings of the row and column address strobes are
automatically modified during an SBE transfer (page 3-15 under
"RAS/CAS Generator"):
The SBE signal will switch the timings of RAS/CAS generators
to perform the required SBE timings. R¯ĀS¯0,1 will be forced
low for the entire SBE transfer and C¯ĀS¯0,1 will be activated
alternately during the SBE transfer (corresponds to the 51XX
family Ripple Mode).
Read and write cycle timing diagrams (pages 3-31 and 3-32) show
the row address strobe asserted and the column address strobe
asserted and deasserted to read and write.
51C64H
"51C64H" describes a 51C64H 64K x 1 bit CHMOS DRAM with a
Ripplemode mode of operation. The 51C256H is one of the 51XX
family of DRAMs supported by the 82C08 DRAM controller.
Ripplemode is a page mode type of memory access. "Ripplemode
operation permits all 256 columns within a selected row of the
device to be randomly accessed at a high data rate. Maintaining
R¯ĀS¯ low while successive C¯ĀS¯ cycles are performed, retains the
row address internally, eliminating the need to reapply it."
(Page 2-19). "Ripplemode operation provides a sustained data
rate of over 18 MHz for applications that require high data rate
such as bit mapped graphics or high speed signal processing."
(Pages 2-19 to 2-20.)
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