Appeal No. 2006-2217 Reexamination Control Nos. 90/006,789 and 90/007,420 to the new page of memory location into which data can be written again at high speeds. The page boundary is detected from a carry bit as the addresses are incremented, after which a full memory cycle is caused to occur, providing a new row and column address (col. 4, lines 3-11; col. 7, lines 28-41; col. 8, lines 50-68; col. 12, line 63, to col. 13, line 5; Fig. 3 "carry" provides "row cycle request" for incrementing row; Fig. 9). Bruce also discloses a page mode memory controller (Figs. 3 and 8, described throughout the patent), which is responsive to a page crossing detection, and states that "many different suitable logic circuits for performing the same functions could be designed by a person skilled in the art" (col. 11, lines 32-34). Differences The differences are described in the analysis. Level of ordinary skill in the art The level of ordinary skill in the art is evidenced by the references. See In re Oelrich, 579 F.2d 86, 91, 198 USPQ 210, 214 (CCPA 1978) ("the PTO usually must evaluate both the scope and content of the prior art and the level of ordinary skill solely on the cold words of the literature"); In re GPAC Inc., 57 F.3d 1573, 1579, 35 USPQ2d 1116, 1121 (Fed. Cir. 1995) (the Board did not err in adopting the approach that the level of skill in the art was best determined by the references of record); Okajima v. Bourdeau, 261 F.3d 1350, 1355, 59 USPQ2d 1795, 1797 (Fed. Cir. 2001) ("[T]he absence of specific findings on the level of skill in the art does not give rise to reversible error 'where the prior art itself reflects an appropriate level and a need for testimony is not shown.'"). Skill in the art is presumed. See In re Sovish, 769 F.2d 738, 743, 226 USPQ 771, 774 (Fed. Cir. 1985). "82C08," "51C64H," and Bruce indicate that those of ordinary skill in the art knew the advantages of page mode memory access and knew how to design page mode DRAMs and page mode DRAM memory controllers. Persons of ordinary skill had sufficient skill to implement the requesting and replying agents to carry out the transfer protocols described in "Multibus II." For example, "iSBC MEM/3XX" discloses a memory requesting agent board including dual ports for access to iPSB and iLBX II buses, and a memory controller for a access to a cache-based memory; the claims are directed to a simpler replying agent with a single bus and no cache memory. The level of skill in the art is also evidenced by the level of disclosure in the '645 patent. Figure 5 of the '645 patent shows Multibus II signals going into a block for the memory - 20 -Page: Previous 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 NextLast modified: November 3, 2007