Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
See Page 3-15.
the control signals comprising "82C08" asserts row address
at least a row address strobe strobes, R¯ĀS¯0 and R¯ĀS¯1, for two
signal associated with a memory banks, and column address
row address and a column strobes, C¯ĀS¯0 and C¯ĀS¯1, for two
address strobe signal banks. See Page 3-15.
associated with a memory column
address; and
means for detecting a "Multibus II" teaches that the
completion of the access to the "replying agent" detects an
memory, the completion "end-of-cycle (EOC)" signal
detecting means being from the "requesting agent"
responsive to an end of access during the reply phase and
control signal generated by the thereafter halts access to the
requesting agent, the access memory. See signal SC2*
completion detecting means (sheet 2-23) and description of
being coupled to the memory transfer cycle at sheets 2-44
address control signal through 2-49.
asserting means for halting the
operation thereof after the end "82C08" detects completion of
of access control signal is the SBE transfer cycle when the
detected; and wherein status lines become inactive.
See Page 3-15.
the memory address control "82C08" describes an SBE
signal asserting means asserts transfer, which is the same as
the memory address control a "page mode" access, by
signals by asserting the row asserting the row address
address strobe in conjunction strobe during the entire SBE
with a row address being transfer cycle and asserting
indicative of a page of data and deasserting the column
within the memory, and address strobe. See
thereafter asserts and Pages 3-15, 3-16, 3-32, & 3-33.
deasserts a plurality of times "82C08" also automatically
the column address strobe increments the column address
signal in conjunction with a internally (page 3-15), as is
plurality of column addresses required by a "replying agent"
for performing a page mode type in "Multibus II" (sheet 2-58).
of memory access.
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Last modified: November 3, 2007