Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
indication. With the EOC, the requesting agent releases
ownership of the bus if other agents request access to the
bus. Otherwise, the agent keeps ownership of the bus.
Signal descriptions
The Parallel System bus contains five groups of signals over
which the requesting and replying agents can enact the protocol
(sheet 2-15). Only the "Address/Data Bus Signal Group" and the
"System Control Signal Group" are relevant here; note that all
groups are discussed in the '645 patent at column 4, line 37 to
column 5, line 22. "Only the requesting agent that is the bus
owner and the selected replying agent(s) use the address/data
signals on the Parallel System bus." (Sheet 2-16.) The
address/data bus signal group includes two sets of signals:
address/data signals and parity signals. We only discuss the
address/data signals. Address/data signals AD31* through AD0*
serve a dual purpose depending on the phase of the transfer
cycle. During the request phase of the transfer, the signals
contain the address for the ensuing transfer cycle, and during
the reply phase of the transfer, the signals contain either 8,
16, 24, or 32 bits of data (sheet 2-17).
The system control signal group consists of a set of ten
signals, SC9* through SC0*, that provide control between agents
during a transfer cycle (sheet 2-17). During the request phase,
the requesting agent drives SC9* through SC0* to provide command
information to the replying agent(s) (sheet 2-18). During the
reply phase of a transfer cycle, the requesting agent drives the
SC9*, SC3*, SC2*, SC1*, and SC0* signals and the replying agent
drives the SC8* through SC4* signals to provide handshake and
status signals (id.). For example, during the request phase,
SC0* indicates a request, SC3* and SC2* identify the width of the
data as 8-, 16-, 24-, or 32-bit transfers, SC4* and SC5* indicate
a memory access, and SC6* indicates whether the operation is a
read or a write (sheet 2-22). During the reply phase, SC2*
indicates an end-of-cycle (EOC) when low and not EOC when high,
SC3* provides a requesting-agent-ready indication on the bus
(part of the reply phase handshake), and SC4* provides a
replying-agent-ready indication on the bus (part of the reply
phase handshake) (sheet 2-23). An agent recognizes the
difference between a one-transfer operation and a sequential
transfer operation by inspecting the handshake signals on SC2*,
SC3*, and SC4* (sheet 2-48).
Bus protocol
The Parallel System bus protocol supports both a
"single-transfer operation" (sheets 2-45 through 2-47) for a
single data transfer, and a "sequential-transfer operation"
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