Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
use page mode access (Br41). It is argued that a person
attempting to redesign the iSBC MEM/3XX board for a page mode of
memory access "would face substantial complexities stemming from,
and incompatibilities between the new circuitry and the existing
memory board" (Br42). "One such source of incompatibility is
within the cache memory subsystem on the iSBC MEM/3xx memory
board" (id.) because if the 2164 DRAMs are accessed in page mode
the memory board must ensure that the cache access method is
compatible or the cache subsystem may function improperly. It is
also argued that the Hoffman declaration states that cache allows
the use of inexpensive and relatively slow DRAM and that a person
skilled in the art would have "realized that choice by the memory
board manufacturer of using a cache implied that adding faster
DRAM or page mode DRAM would have had little or no effect on
performance" (id.). It is argued that timing and programming for
page mode control signals are not taught and "[w]ithout any such
teaching, a person of ordinary skill in the art would be left
simply to guess at a correct timing sequence for page mode
operations to provide a 'memory address control signal asserting
means' that is capable of 'performing a page mode type of memory
access'" (Br43). It is argued that "the re-design would have to
avoid interfering with the chip's capability to access and
interface properly with other components on the memory board as a
whole" (id.). It is lastly argued that page mode access requires
storage functionality that is not taught by the references (id.).
The examiner responds (EA14-15):
[O]ne of ordinary skill in the art would not face
substantial complexities in adding the functionality of
accessing the 2164A DRAM memories of the iSBC MEM/3xx memory
board. The fact that the memory board may perform other
functions (i.e. caching, as cited in the Hoffman
declaration) does not create a barrier to adding the
functionality of page mode accessing the 2164A DRAMs.
The examiner responds that patent owner's arguments "seem to
suggest that one of ordinary skill in the art could have easily
identified the necessary modification(s) to the iSBC memory board
that would have been required to add the page mode access
functionality" (EA15).
Patent owner replies that the examiner improperly uses the
appeal brief as evidence to suggest that there would have been a
reasonable expectation of success (RBr10).
Initially, we think that "reasonable expectation of success"
is a concept limited to unpredictable arts, such as chemistry and
biotechnology, and does not apply the electrical or mechanical
arts where whether something will work as designed is almost
never in issue. Thus, we interpret patent owner's arguments as
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