Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
operation thereof after the end
of access control signal is
detected; and wherein
the memory address control The iSBC MEM/3XX memory board
signal asserting means asserts in "286/100" uses 2164 DRAMs.
the memory address control See "iSBC MEM/3XX," Fig. 10-2,
signals by asserting the row p. 10-29. 2164 DRAM chips have
address strobe in conjunction a page mode of memory access.
with a row address being
indicative of a page of data
within the memory, and Difference: None of "286/100,"
thereafter asserts and "Multibus II," and
deasserts a plurality of times "iSBC MEM/3XX" discloses a
the column address strobe memory controller controlling
signal in conjunction with a DRAMs in a page mode of access.
plurality of column addresses
for performing a page mode type
of memory access.
The examiner finds and addresses the difference between the
collective teachings of "286/100," "Multibus II," and
"iSBC MEM/3xx" as follows (FR5):
"286/100" (as supported by "[iSBC MEM/3XX]") does not
specifically teach that the 2164 DRAM chips of the iSBC®
MEM/3xx memory board are selected to be utilized in the page
mode (wherein page mode [operates as claimed]). However, it
would have been obvious to one of ordinary skill in the art
to have utilized the page mode operation of the 2164 DRAM
chip on the iSBC® MEM/3xx memory board in the system of
"286/100" because "2164A" teaches on page 3-278, right
column, second paragraph under "Page Mode Operation" that
page mode operation allows a maximum data transfer rate.
"2164A" is used only for its description of the advantage of a
page mode of operation. There is no dispute that 2164 DRAMs have
the same page mode as in "2164A.".
Patent Owner argues that the examiner errs in finding that
"286/100" and "2164A" teach the follow elements (Br30):
(1) "memory address control signal asserting means . . . for
performing a page mode type of memory access"
(claim 1), or "asserting a plurality of memory address
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