Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
replying agent, the request initiating access to memory on
detecting means being coupled the replying agent. E.g.,
to a system bus, and request Sheet 2-10. The request for
being made over the system bus access is made over the system
by a requesting agent; bus by a requesting agent using
the bus system control signals
SC9* through SC0* (sheets 2-17
through 2-22) and the bus
address/data signals AD31*-AD0*
(sheet 2-17).
means, responsive to the "286/100" and "Multibus II" do
request detecting means not teach specifics of how a
detecting the request, for "replying agent" performs a
asserting a plurality of memory memory access.
address control signals for
accessing a plurality of times In "iSBC MEM/3XX," "the
the memory on the replying Controller Subsystem provides
agent, the control signals the control logic necessary to
comprising at least a row perform transfer cycles on the
address strobe signal iPSB and iLBX buses" (p. 2-5),
associated with a memory row where "transfer cycles" include
address and a column address memory accesses. The cache
strobe signal associated with a memory controller (CMC) gate
memory column address; and array logic controls the iPSB
and iLBX II bus interfaces, and
controls and initializes the
cache and DRAM arrays
(Figure 2-1; p. 2-6). The DRAM
arrays are controlled using row
address strobe logic and column
address strobe logic
(Figure 2-1; p. 2-3).
means for detecting a "Multibus II" teaches that the
completion of the access to the "replying agent" detects an
memory, the completion "end of cycle (EOC)" signal
detecting means being from the "requesting agent"
responsive to an end of access during the reply phase and
control signal generated by the thereafter halts access to the
requesting agent, the access memory. See signal SC2*
completion detecting means (sheet 2-23) and description of
being coupled to the memory transfer cycle at sheets 2-44
address control signal through 2-49.
asserting means for halting the
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