Ex Parte 4918645 et al - Page 4




         Appeal No. 2006-2217                                                       
         Reexamination Control Nos. 90/006,789 and 90/007,420                       

              Bruce                   4,546,451       October 8, 1985               
              iSBC® 286/100 Multibus® II Single Board Computer,                     
              Intel Corp., March 1985 ("286/100").                                  
              2164A Family, 65,536 x 1 Bit Dynamic RAM, April 1982,                 
              Intel Corp., pages 3-267 to 3-279 ("2164A").                          
              Multibus® II Bus Architecture Specification Handbook,                 
              Intel Corp., 1984 ("Multibus II").                                    
              iSBC® MEM/312/310/320/340 Memory Boards User's Guide,                 
              Intel Corp., February 1985 ("iSBC MEM/3XX").                          

                                   THE REJECTIONS                                   
              Pages of the final rejection entered July 20, 2005, are               
         referred to as "FR  " and pages of the examiner's answer entered           
         December 21, 2005, are referred to as "EA  ."  Pages of the                
         Patent Owner's brief received October 11, 2005, are referred to            
         as "EA  " and pages of the reply brief received February 8, 2006,          
         are referred to as "RBr  ."                                                
              Claims 1 and 12 stand rejected under 35 U.S.C. § 103(a) as            
         being unpatentable over "286/100" and "2164A."  "Multibus II" and          
         "iSBC MEM/3XX" are used as extrinsic evidence to support inherent          
         features of the system described in "286/100."                             
              Claims 6 and 17 stand rejected under 35 U.S.C. § 103(a) as            
         being unpatentable over "286/100," "2164A," and Bruce.  Since              
         claims 6 and 17 contain the limitations of claims 1 and 12,                
         respectively, the rejection impliedly also relies on                       
         "Multibus II" and "iSBC MEM/3XX."                                          

                                     DISCUSSION                                     
         Claim interpretation                                                       
              We accept and incorporate by reference the definitions of             
         claim terms in Patent Owner's "Summary of Claimed Subject Matter"          
         (Br7-26) for purposes of this appeal.  Because the definitions             
         are based on the Multibus II standard in the document High                 
         Performance 32-Bit Bus Standard P1296 (unapproved draft), IEEE,            
         June 20, 1986, which is incorporated in the '645 patent (col. 3,           
         lines 51-56), which in turn is based on the Multibus II standard           
         in "Multibus II" in the rejection, the definitions are not at              
         issue.                                                                     
              With respect to apparatus claims 1, 2, and 6, Patent Owner            
         states that the means for performing the function of "detecting a          
         request for initiating an access to a memory on the replying               
         agent" is "circuitry within or associated with the memory                  
                                       - 4 -                                        





Page:  Previous  1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  Next 

Last modified: November 3, 2007