Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
use" interpretation, e.g., the "memory address control signal
asserting means" in the last paragraph produces row and column
address strobe signals, but does not positively require that the
signals access a memory. However, the first subparagraph of the
claim body recites "the request detecting means being coupled to
a system bus, and request being made over the system bus by a
requesting agent," which positively recites at least a system bus
in combination with the memory control apparatus and requires
that the request come from a requesting agent as defined in the
preamble. A similar issue exists with respect to whether method
claims 12, 13, and 17 claim the method for controlling a memory
alone or as part of a method on a data processing system. To
avoid these claim interpretation issues, we assume that the
memory controller apparatus and method for controlling a memory
require a requesting agent and replying agent electrically
coupled together by a system bus. That way, if the claims
require less, they are still met.
Examiner's rejection
The "286/100," "Multibus II," and "iSBC MEM/3XX" references
collectively describe a data processing and memory system using
the Multibus II bus architecture and protocols. "Multibus II"
describes the terminology, structure, and bus protocol of the
Intel Multibus II Parallel System bus iPSB shown in "286/100,"
and "iSBC MEM/3XX" describes the structure of the iSBC MEM/3XX
memory board shown in "286/100." A claim chart comparing claim 1
to the system collectively described in "286/100," "Multibus II,"
and "iSBC MEM/3XX" is shown below.
Claim 1 Collective teachings of
"286/100," "Multibus II,"
and "iSBC MEM/3XX"
1. Memory control apparatus for "Multibus II" teaches
use in a data processing system "requesting agents" and
having at least a requesting "replying agents" electrically
agent and said [sic] replying coupled by an iPSB Parallel
agent electrically coupled System bus (Figure 1-2;
together by a system bus, sheet 2-6).
Figure 1 of "286/100" teaches a
"requesting agent" (286/100
single board computer) and a
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