Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
(sheets 2-48 through 2-49), for multiple data transfers. "The
sequential transfers are terminated by an end-of-cycle indication
from the requesting agent." (Sheet 2-48.)
The tasks of the replying agent during sequential access are
described as follows (sheet 2-58):
4) The replying agent must increment the initial address
given by the requesting agent to obtain the address for
subsequent accesses of data when performing a transfer
cycle that requires sequential accesses of memory.
5) For sequential-access operations, the address
incrementing algorithm varies depending on the data
width that is required by the requesting agent. For an
8-bit transfer, the address is incremented by one at
each access; for a 16-bit transfer, the address is
incremented by two at each access, and so on. Refer to
Figure 3-20.
82C08
"82C08" describes the 82C08 DRAM controller. "The Intel
82C08 Dynamic RAM Controller is a microcomputer peripheral device
which provides the necessary signals to address, refresh, and
directly drive 64K and 256K dynamic RAMs." (page 3-4 under
"General Description"). "The 82C08 supports Sequential Bus
Extension (SBE) systems. By taking advantage of the Intel DRAM
Ripplemode and SBE it performs high rate block data transfer
which increases the bus bandwidth by about three times the
iAPX 186 bandwidth." (Id.) "82C08" states that "[t]he 82C08 has
control circuitry capable of supporting one of several possible
bus structures" (page 3-4 under "Processor Interface").The SBE is
a "superset" of the iAPX 80186/188 (186/188) bus, i.e., it
contains elements in addition to those the 186/188 bus, but
components designed for the 186/188 bus will also operate with
the SBE. The advantages of SBE transfer are (page 3-15, under
"Introduction"):
The SBE transfer allows consecutive words (bytes) of data to
be transferred on consecutive clock cycles. The SBE aims to
increase the bus bandwidth by 2.91 to 3.36 times the 186/188
bus, and to allow block transfer between MULTIBUS II and the
186/188 bus. SBE will support the 51XX CMOS DRAM's [sic,
DRAMs] .... For READ cycles, the SBE will support the
RIPPLEMODE feature of the 51XX family ....
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