Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
address/data lines AD31*
through AD0* of the system bus.
The "replying agent" responds
by sending or receiving data
over the address/data lines of
the system bus. See
description of transfer cycle
at sheets 2-44 through 2-49.
"82C08" receives a request for
access to memory and can
support a bus. See 3-4.
means, associated with a "Multibus II" teaches that the
replying agent, for detecting a "replying agent" detects a
request for initiating an command for initiating access
access to a memory on the to memory on the replying
replying agent, the request agent. E.g., Sheet 2-10. The
detecting means being coupled "replying agent" is coupled to
to a system bus, and request the system bus (Figure 1-2,
being made over the system bus sheet 2-6). The request for
by a requesting agent; access is made over the system
bus by a requesting agent using
the bus system control signals
SC9* through SC0* (sheets 2-17
through 2-22) and the bus
address/data signals AD31*-AD0*
(sheet 2-17).
"82C08" detects a request for
access to memory when status
lines become active. See
Page 3-15.
means, responsive to the The "replying agent" in
request detecting means "Multibus II" inherently must
detecting the request, for have means for asserting memory
asserting a plurality of memory address control signals for
address control signals for sequentially accessing memory a
accessing a plurality of times plurality of times. See
the memory on the replying Sheet 2-58.
agent,
"82C08" asserts row and column
address strobe signals and
column memory address signals.
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