Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
look to Intel products, such as the "82C08," because they are
more likely to have been designed to work together.
We find that the level of knowledge of those of ordinary
skill in the art was sufficient to enable one skilled in the art
to interface the "82C08" memory controller to the "Multibus II"
system bus and replying agent. The best evidence of this is that
the '645 patent does not provide any circuit details of the
memory controller: it merely shows Multibus II signals going into
a block for the memory controller 66 having an internal
decoder 70 and a memory access control (timer 78, counter 80,
compare 82, and refresh control are not relevant to claim 1) with
no circuitry showing how the signals are used to perform the
functions. Since the '645 patent provides no details of the
memory controller 66, decoder 70, and memory access control, it
must be assumed that one of ordinary skill in the computer art
possessed the required knowledge to implement a page mode memory
controller using Multibus II control signals or patent owner's
own disclosure would be nonenabling. See In re Epstein,
32 F.3d 1559, 1568, 31 USPQ2d 1817, 1823 (Fed. Cir. 1994)
("Rather, the Board's observation that appellant did not provide
the type of detail in his specification that he now argues is
necessary in prior art references supports the Board's finding
that one skilled in the art would have known how to implement the
features of the references and would have concluded that the
reference disclosures would have been enabling."); In re Fox,
471 F.2d 1405, 1407, 176 USPQ 340, 341 (CCPA 1973) (appellant's
specification "assumes anyone desiring to carry out the process
would know of the equipment and techniques to be used, none being
specifically described"); Constant v. Advanced Micro-Devices,
Inc., 848 F.2d 1560, 1569, 7 USPQ2d 1057, 1063 (Fed. Cir. 1988)
("The disclosure in Exhibit 5 is at least of the same level of
technical detail as the disclosure in the '491 patent. If
disclosure of a computer program is essential for an anticipating
reference, then the disclosure in the '491 patent would fail to
satisfy the enablement requirement of 35 U.S.C. § 112, First
¶."). In addition, however, we find that the level of ordinary
skill in the Multibus II and memory controller arts was very
high, as evidenced by the references, and that those skilled in
the art had the knowledge and experience to interface the "82C08"
with the "Multibus II" replying agent and system bus. Those
skilled in the art of the "Multibus II" bus architecture knew how
to design requesting agents, replying agents, system bus, and
memory to satisfy the electrical, mechanical, and protocol
interface requirements of the Multibus II standard, as evidenced
by "Multibus II" and "iSBC MEM/3XX." "Multibus II" indicates
initiation of a sequential transfer when the SC2* signal is not
asserted by the requesting agent during the reply phase, and
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