Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
EOC signal when asserted (active). One of ordinary skill would
have had sufficient skill to interface these two sets of signals.
Patent Owner also argued that the rejection improperly
reduces the invention to a mere "idea" (RR11):
Further, relying on the isolated reference to
Multibus II (page 3-15) and general description of
advantageous features in the 82C02 [sic] (page 3-1) to
support the particular combination of the 82C02 [sic] with
the iPSB, despite no teaching of a detection of the signal
(SC2*) that allegedly corresponds to the end of access
signal, improperly reduces the claimed invention to an [sic]
mere "idea" of an end of access signal and a page mode, and
thus, does not consider the claimed invention as a whole.
Reducing a claimed invention to an "idea," and then
determining patentability of that "idea" is an error. Jones
v. Hardy, 727 F.2d 1524, 1528, 220 USPQ 1021, 1024 (Fed.
Cir. 1984); W.L. Gore & Associates, Inc. v. Garlock, Inc.,
727 F.2d 1524, 1528 [sic, 721 F.2d 1540, 1547-48],
220 USPQ 303, 308-09 (Fed. Cir. 1983).
The rejection is not based on finding the page mode and an
end of access signal to be the "gist" or "thrust" of the
invention. "Multibus II" discloses the protocol for a memory
replying agent, which detects non-final and final (end-of-cycle)
memory accesses with the SC2* signal, but does not disclose how
the memory and memory controller is implemented. One of ordinary
skill in the art seeking to implement a memory and memory
controller for a memory replying agent in "Multibus II" would
have been motivated to select a commercial memory and memory
controller with a page mode of access, such as "51C64H" and
"82C08," for the known speed advantages of page mode. "82C08"
detects the start and end of page mode access.
Claims 6 and 17
Claim 6 contains all of the limitations of claim 1, plus the
following limitations:
means for detecting a memory page boundary having
inputs coupled to the memory column address and an output
expressive of a state of the memory column address that is
indicative of a memory page boundary; and
means, responsive to the output of the memory page
boundary detecting means, for deasserting the row address
strobe signal, providing a memory row address expressive of
another page of data, and reasserting the row address strobe
signal.
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