Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
lines 24-30). The invention is summarized in Churchward as
follows (col. 3, lines 31-48):
In order to allow for such relatively long memory
access cycle times, and to prevent the refresh cycle
requirements from unduly interfering with the access to the
memory for normal reading and writing, a stockpile counter
is employed which "stores" up to eight refresh cycle counts.
During times that the memory is "busy", (i.e. while a
requestor device is requesting memory access for either
reading or writing), the counter counts down toward zero.
Thus, if a refresh request occurred immediately prior to the
time that the memory became busy, the next refresh requests
at 15.6 microseconds apart are ignored, for as long as the
memory remains busy up to a total of eight. However, upon
the occurrence of the ninth refresh request, refreshing
becomes mandatory and continues every 15.6 microseconds as
long as the memory remains busy. If the memory becomes not
busy before a zero count is reached, it counts back towards
a count of eight at a 450 nanosecond rate.
With this timing cycle, there will be a delay period of
up to 125 microseconds, during which time if the memory
remains busy the refresh requests will be initiated, but
ignored, until such time that the counter that stores the
refresh bank has counted down to zero, at which count
refreshing becomes mandatory.
The refresh scheme is illustrated in Fig. 2. Normally, rows
are refreshed every 15.6 microseconds shown by the equally spaced
hash marks. A refresh takes about 450 nanoseconds to read and
write a row. When the memory becomes busy, the refresh cycle is
locked out for up to eight cycles (8 cycles x
15.6 microseconds/cycle = 124.8 microseconds) indicated by the
"count." When the count equals zero, refreshing becomes
mandatory at the 15.6 microsecond rate; note that, although not
shown, memory access is suspended during the refresh time. When
the memory becomes not busy, a number of rows equal to the stored
count are refreshed at the 450 nanosecond rate.
Churchward has a refresh counter 62 which recycles every
15.6 microseconds in response to clock 51 (Fig. 1b; col. 6,
lines 13-15), which corresponds to the "means for generating a
memory refresh request signal at predetermined intervals."
Churchward has a stockpile up/down counter 96 (Fig. 1c), but
it only counts refresh requests signals when the memory is busy.
The structure corresponding to the "means for counting,"
counter 80 if Fig. 5, counts every refresh request signal, so a
circuit which only counts when the memory is busy is not
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