Ex Parte 4918645 et al - Page 32




         Appeal No. 2006-2217                                                       
         Reexamination Control Nos. 90/006,789 and 90/007,420                       


              "82C08" discloses that during the SBE transfer mode                   
         (corresponding to the claimed "page mode"), the column address is          
         incremented by an internal address counter (page 3-15 and                  
         "Address Latch and Address Counter" on page 3-16).  "An overflow           
         of the COLUMN address counter will generate an overflow signal             
         which will disable SRDY and SBE signals (it will actually                  
         terminate the SBE transfer)."  (Page 3-15.)  The overflow signal           
         indicates a page address boundary (i.e., the end of a row).                
         Thus, "82C08" teaches structure "for detecting a memory page               
         boundary."  However, "82C08" teaches that the SBE transfer mode            
         (page mode) is terminated upon reaching page boundary.                     
              Bruce discloses a page boundary crossing technique during a           
         page mode of operation.  The page boundary is detected from a              
         carry bit as the addresses are incremented, after which a full             
         memory cycle is caused to occur, providing a new row and column            
         address (e.g., col. 4, lines 3-11; col. 8, lines 50-68).  Bruce            
         discloses how the page boundary hardware in interfaced to a page           
         mode memory controller and actually discloses a page mode memory           
         controller (Figs. 3 and 8).  This hardware is the same or                  
         equivalent to the structure corresponding to the "means for                
         detecting" and "means for deasserting and reasserting" in the              
         '645 patent.  One of ordinary skill in the art would have been             
         motivated to modify "82C08" to provide structure deasserting the           
         row address strobe signal, changing the memory row address, and            
         reasserting the row address strobe signal in order to achieve the          
         advantage of crossing a page boundary as taught in Bruce.                  
              Patent Owner argues that Bruce teaches one to reorganize              
         data so that a row or page of the DRAM stores the data                     
         corresponding to a two-dimensional cell of a display, instead of           
         the customary single row of pixels, which requires extensive and           
         complex additional circuitry (Br48).  It is argued (id.):                  
              Bruce teaches expressly that its invention becomes useful             
              only after this non-trivial reorganization.  See id. at               
              col. 8:6-10  Thus, Bruce teaches away from using its page             
              boundary detection technique in a non-graphics display DRAM           
              system . . . (i.e., in systems where a page is not mapped to          
              a system using a two-dimensional region on a display                  
              screen).                                                              
              Bruce's teaching of page boundary detection and page                  
         boundary crossing during a page mode memory operation is                   
         described as general solution for page mode operation.  Nowhere            
         does Bruce state or imply that the page crossing technique only            
         is useful when used with the particular memory organization.               
              Patent Owner argues that Bruce is not analogous art that can          
         properly be combined because it relates to graphics constraints            
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