Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
determining when a number of counted refresh request signals
equals or exceeds the predetermined threshold value; and
means, responsive to the comparing means determining
that a number of counted refresh request signals at least
equals the predetermined threshold value, for refreshing a
plurality of memory rows, the number of memory rows being
refreshed being substantially equal to the counted value.
It is helpful to understand prior art refresh techniques,
which are described in "AP-97A" at page 3-116. Typically, each
row of a DRAM must be refreshed every 2 milliseconds (ms) or the
data in it will be lost. In a "distributed refresh" method for a
DRAM with 128 rows and 128 columns, a single refresh cycle is
performed every 2 ms/128 = 15.6 microseconds. "AP-97A" also
describes a "burst refresh" method:
Burst refresh means waiting almost 2 ms from the last time
refresh was performed, then refreshing the entire memory
with a "burst" of 128 refresh cycles. This method has the
inherent disadvantage that during the time refresh is being
performed (more than 40 microseconds for 128 rows) no read
or write cycles can be performed. This severely limits the
worst case response time to interrupts and makes this
approach unsuitable for many systems.
The refresh technique of the '645 patent is "burst refresh"
of less than all of the rows. The '645 patent explains that a
timer generates a refresh request at predetermined intervals.
The refresh requests are counted by a refresh request counter and
a comparator determines when the count equals or exceeds a
predetermined threshold value, such as 24, at which time it will
attempt to burst refresh all of the pending 24 requests. This is
recited in claims 2 and 13. The prior art "burst refresh" does
not need to count memory refresh request signals because all rows
are refreshed. If a bus transfer is in progress, the memory
controller will attempt to wait until the bus transfer is
completed. But, if some maximum number of requests are pending,
such as 41, the bus transfer is interrupted and a burst refresh
of the number of requests in the count is performed. This
"blocked refresh" technique is in claims 4 and 15. See Col. 8,
lines 35-61. The technique has the advantage of not tying up the
memory as long as the prior art "burst refresh" of all rows.
Churchward discloses that a nominal read-write access memory
cycle is on the order of 450 nanoseconds, but certain memory
cycles may require up to 10 microseconds which is a large
fraction of the normal refresh time of 15.6 microseconds (col. 3,
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