Ex Parte 4918645 et al - Page 41




         Appeal No. 2006-2217                                                       
         Reexamination Control Nos. 90/006,789 and 90/007,420                       

         The motivation springs from the fact that some kind of memory and          
         memory controller must be used...                                          
         **  One of ordinary skill in the art seeking to design a memory            
         replying agent would have been motivated to use DRAM for its               
         known advantages (higher packaging density, lower cost per bit,            
         and lower power), as taught by "AP-97A" (page 3-111), and because          
         "iSBC MEM/3XX" expressly discloses DRAM memory in a Multibus II            
         memory replying agent.  "51C64H" was a known DRAM chip and                 
         "82C08" was a known DRAM memory controller for this chip.                  
         Although it is evidently presumed by the inventor of the '645              
         patent that one of ordinary skill in the art had sufficient                
         knowledge to enable him or her to build a page mode memory                 
         controller, because no memory controller circuitry is described,           
         "82C08" nevertheless teaches a memory controller for page mode             
         DRAMs.                                                                     


         In particular, "Multibus II" presumes that one of ordinary skill           
         in the art had the knowledge necessary to design a replying agent          
         to detect a request for sequential transfer from the requesting            
         agent during the request and reply phases, and to detect the end           
         of a sequential transfer (the EOC signal on SC2*) from the                 
         requesting agent during a reply phase in order to conduct the              
         Multibus II protocol.                                                      
         *   "82C08" teaches that "[t]he 82C08 has control circuitry                
         capable of supporting one of several possible bus structures"              
         (page 3-4)                                                                 
              AP-97A                                                                
              "AP-97A" discloses that DRAMs have many advantages: four              
         times the density (number of bits per device) of static RAMs,              
         which allows four times as many bytes to be put on a board; the            
         cost per bit is roughly one-fourth that of static RAMs; they use           
         about one-sixth the power of static RAMs, so power supplies may            
         be smaller and less expensive (page 3-111: note that "Third,               
         static RAMs ..." should be "Third, dynamic RAMs ...).                      

              ***??                                                                 
         * In a sequential-transfer operation the requesting agent                  
         provides the address on address/data lines AD31* to AD0* and               
         commands for a transfer, a number of data transfers take place             
         between the replying agent and the requesting agent **** and "             

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