Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
80186 processors; and (c) Intel 80286 processors. [See the
82C08 at pages 3-3, 3-4, 3-9 and 3-10.] It should be noted
that Multibus (a.k.a. Multibus I), which is referred to
throughout the 82C08, has a different bus architecture from
Multibus II and does not include the iPSB bus referenced by
the Office Action. [See, e.g., Multibus II Handbook at
sheet 1-1.] There is no teaching whatsoever in the 82C08
that the 82C08 detects commands or signals from the iPSB of
the Multibus II. For example, the SC2* signal (cited in the
Office Action as corresponding to the "end of access control
signal recited in the claims) from the system control signal
group SC0*-SC9* of the iPSB is not any one of the input
control signals of the 82C08 controller.
Further, page 3-1 of the 82C08 illustrates the pin-outs
and pages 3-2 to 3-3 describes the signals or connections of
each pin-out. As described therein, none of the pin-outs
detect signals from the iPSB bus, including the SC0* and
SC2*, described (e.g., at pages 2-17 to 2-24) in the
Multibus II Handbook.
It is true that "82C08" does not describe how to connect the
82C08 memory controller directly to an iPSB Parallel System bus
and replying agent, as taught in "Multibus II"; e.g., none of the
input pin descriptions (pages 3-2 to 3-3) describe accepting the
SC2* "end of cycle" signal from a "Multibus II" iPSB system bus.
We do not contend that "82C08" could be directly connected to a
system bus in a "Multibus II" memory replying agent without any
interface circuitry. The rejection is based on obviousness and
therefore must take into account the level of skill of a person
of ordinary skill in the art at the time the invention was made.
We have found that a person of ordinary skill in the art had
sufficient knowledge and design experience to enable him or her
to interface the "82C08" to a "Multibus II" memory replying agent
for two reasons. First, the '645 patent itself provides no
details of the memory controller circuitry to convert Multibus II
control signals into page mode control signals: Fig. 5 merely
shows a block diagram of a memory controller 66. This implies
that design of the whole memory controller was within the level
of ordinary skill in the art or the '645 patent would not be
enabled. By contrast, "82C08" discloses a commercial page mode
memory controller and the only design modifications needed are to
interface the inputs to the signals of a replying agent and
system bus. Second, the level of ordinary skill in the
electronics and computer arts was very high, as demonstrated by
the references, and we find that those persons skilled in the art
knew how to interface electrical signals given the interface
specifications despite the fact that the signal names may be
- 28 -
Page: Previous 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Next
Last modified: November 3, 2007