Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
indicates the EOC when SC2* is asserted by the requesting agent
during the final reply phase (sheet 2-48).
"82C08" detects an SBE multiple transfer with the status lines
are active and detects an end of SBE transfer when the status
lines are inactive. Thus, the only interface that seems to be
required is logic to convert detection of SC2* being inactive
during a first reply phase to active status lines in "82C08," and
to maintain the status lines active until an EOC signal is
received. One skilled in the art had to knowledge to interface
very complicated signals given the interface specifications
between the two devices.
Arguments
The examiner entered a rejection over "Multibus II" and
"82C08" in the Office action of May 5, 2004, in the '6789 Reexam,
which are the same references primarily being relied upon in the
new grounds of rejection. Patent Owner replied with Request for
Reconsideration (pages referred to as "RR__") on June 30, 2004,
after which examiner changed the rejection. We have considered
the Patent Owner's arguments.
Patent Owner argued that the combination of "Multibus II"
and "82C08," even if proper, does not teach "means for detecting
a completion of the access to the memory" (claim 1) and
"detecting a logic state of an end of access bus control signal"
(claim 12) (RR4-6). In response to the rejection that it would
have been obvious to one of ordinary skill in the art to have
utilized the "82C08" memory controller in the memory "replying
agent" in Figure 1-2 (sheet 2-6) of "Multibus II", the same basic
reasoning used in the present new ground of rejection, Patent
Owner argued that "82C08" does not show inputs for the
Multibus II control signals (RR5-6):
However, despite the isolated reference to Multibus II in
the 82C08 (page 3-15), one of ordinary skill in the art
would have appreciated that the interface described in the
82C08 (at pages 3-2 and 3-3) does not detect signals from
the iPSB, including the SC0* and SC2*, described (e.g., at
pages 2-17 to 2-24) in the Multibus II Handbook. Therefore
and as discussed at the personal interview, the combination
of the iPSB bus in the Multibus II Handbook and the 92C08
controller, as suggested by the Office Action, does not
establish a prima facie case of obviousness, as required
under Section 103.
More particularly, the signal lines of the 82C08
interface are WRITE (W¯R¯), READ (R¯D¯), and Port Control (PCTL)
[See the 82C08 at page 3-3.] The interface of the 82C08
controller supports: (a) the Multibus; (b) Intel 8086 /
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