Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
controller 66 with an internal decoder 70 and a memory access
control (timer 78, counter 80, compare 82, and refresh control
are not relevant to claim 1) with no circuitry showing how the
signals are used to perform the functions. Since the '645 patent
provides no circuit details of memory controller 66, decoder 70,
and memory access control, it must be assumed that the level of
ordinary skill in the computer art was sufficiently high to
enable implementation of a page mode memory controller using
Multibus II control knowing only the Multibus II protocol and the
necessary page mode control signals.
Objective evidence of nonobviousness
No objective evidence of nonobviousness has been presented.
Claims 1 and 12
The following claim chart shows that "Multibus II" and
"82C08" disclose all elements of claim 1.
Claim 1
"Multibus II" and "82C08"
1. Memory control apparatus for "Multibus II" teaches
use in a data processing system "requesting agents" and
having at least a requesting "replying agents" electrically
agent and said [sic] replying coupled by an iPSB Parallel
agent electrically coupled System bus (e.g., Figure 1-2,
together by a system bus, sheet 2-6). "Replying agents"
with memory inherently have to
have a memory controller.
"82C08" is a memory controller.
the requesting agent requesting "Multibus II" teaches that the
access to a memory on the "requesting agent" sends a
replying agent for storing and request for access to memory
retrieving data therein over over the system control lines
the system bus, the apparatus of the system bus (e.g., SC0*
comprising: indicates a request, SC4* and
SC5* indicate a memory access,
and SC6* indicates whether the
operation is a read or a write,
see sheet 2-22) as well as the
address in memory over the
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