Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
iSBC MEM/3XX
"iSBC MEM/3XX" describes the iSBC MEM/312, /310, /320, and
/340 memory boards (collectively referred to as the iSBC MEM/3XX
boards). The iSBC MEM/3XX board is a high-speed, dual port,
cache-based memory expansion board, which is physically and
electrically compatible with Intel's Multibus II Bus Architecture
Specification (page 1-1). The iSBC MEM/3XX acts as a "replying
agent."
The four versions of the iSBC MEM/3XX board have from 512K
to 4M of DRAM (p. 1-2). Each version of the board has 8 Kbytes
of cache SRAM (static RAM) and 32-bit port interfaces to the
Parallel System bus (iPSB bus) and the Local Bus Extension Bus
(iLBX II bus) (id.). The DRAM subsystem consists of memory
address and write enable logic, row address strobe (RAS) logic,
column address strobe (CAS) logic, and parity detection logic
(pp. 2-3 to 2-4). The controller subsystem generates the control
signals and timing for the iSBC MEM/3XX board, provides the
control logic necessary to perform transfer cycles on the iPSB
and iLBX II buses, and performs on-board functions, such as
refresh and initialization (p. 2-5). The memory uses 2164 DRAMs
(e.g., Fig. 10-2, p. 10-29, identified as "DR 2164").
Bruce
Bruce discloses that DRAMs have the advantages of "low cost,
large number of storage locations or 'bits,' small size, low
power consumption and reasonable read and write access times"
(col. 1, lines 65-68). Bruce discloses that DRAM manufacturers
have provided a "page mode" of access where "[o]nce any memory
location within the page has been accessed at normal access
speeds, any other memory location on the same page can be
accessed at significantly higher speeds than a normal access to
an arbitrary memory location by changing only the column address"
(col. 2, lines 12-17). The problem with using page mode in
raster graphics memory systems is that graphics information is
two dimensional while pages are arranged in only one dimension
(col. 2, lines 17-23). Bruce discloses an addressing technique
to that storage locations on a page form a contiguous "cell"
corresponding to a region of the displayed image, which allows
writing using the high speed page mode of operation (col. 3,
lines 35-44).
Bruce discloses a page boundary crossing technique during a
page mode of operation (col. 3, lines 44-51):
When a page boundary is crossed, one slower memory access is
required to get on the new page, and the invention provides
a technique for detecting the crossing of a page boundary to
allow the initial full memory cycle required to gain access
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