Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
It is noted that claim 1 does not require a DRAM, but only
requires the memory control apparatus to provide control signals
to perform a page mode access.
The differences between the subject matter of claim 1 and
"Multibus II" are that while the "replying agent" taught by
"Multibus II" must inherently have "memory address control signal
asserting means" (i.e., a memory controller) to sequentially
access memory, it does not teach utilizing "control signals
comprising at least a row address strobe signal ... and a column
address strobe signal" and therefore also does not teach that it
"asserts the memory address control signals by asserting the row
address strobe ... and thereafter asserts and deasserts a
plurality of times the column address strobe signal ... for
performing a page mode type of memory access." Not all types of
memories require row and column address strobe control signals.
Row and column address strobe signals and the claimed "page mode"
type of memory access inherently imply a DRAM.
"82C08" describes a DRAM memory controller which detects
when the status lines become active, indicating the beginning of
an SBE transfer mode for initiating an access to memory; provides
page mode memory access control signals (i.e., asserting the row
address strobe and asserting and deasserting the column address
strobe) during the SBE transfer mode; and detects when the status
lines become inactive, indicating an end of access control
signal. Since the '645 patent does not disclose any structure
for performing the functions of the "means-plus-function"
limitations, but only shows a memory controller block 66 and a
memory access control block, any structure is "the corresponding
structure ... described in the specification and equivalents
thereof" under 35 U.S.C. § 112, sixth paragraph. Thus, "82C08"
meets the "means-plus-function" limitations of claim 1. The
differences between the subject matter of claim 1 and "82C08" are
that "82C08" does not teach that the memory controller is
associated with a "replying agent" which is coupled to a system
bus to receive the request from a "requesting agent."
One of ordinary skill in the art would have been motivated
to utilize the "82C08" DRAM memory controller in the memory
"replying agent" in Figure 1-2 (sheet 1-9) of "Multibus II" to
provide for "page mode" memory access for several reasons.
First, "Multibus II" describes a bus protocol, but leaves it to
designers of ordinary skill in the art to design the requesting
agent and replying agent hardware to implement the protocol: one
of ordinary skill in the art seeking to design a memory replying
agent would have been motivated to use any commercial type of
memory, such as the "51C64H" DRAM, and any commercial type of
memory controller, such as the "82C08." **Those of ordinary
skill in the art of computer system architecture had sufficient
knowledge and skill to implement the Multibus II requesting agent
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