Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
analysis of the claimed invention by the parts, not by the
whole. That is what seems to have happened here.
Again, the issue is obviousness, not whether "82C08"
discloses how to directly couple an 82C08 memory controller to
the memory replying agent and system bus in "Multibus II." Since
there is motivation for combining "82C08" with "Multibus II," the
analysis is proper.
Patent owner argued that the rejection improperly relies
upon picking and choosing and involves impermissible hindsight
(RR10):
For example, the Patent Office relies upon a general
statement of principle indicated in the 82C08 Advance
Datasheet that "the SBE aims to increase the bus bandwidth"
and an isolated" statement from a datasheet having numerous
other sections "to allow block transfer between the
MULTIBUS II and the 186 / 188 bus." [See the 82C08 at
page 3-15 (INTRODUCTION).] However, since the command
signals, including the SC2*, on the iPSB are not detected by
the 82C08 controller, the SC2* signal (which allegedly
corresponds to the "end of access system bus control
signal") on the iPSB would not, and could not, be used to
cause the 82C08 controller to end access to DRAM.
Since the Patent Office picked and chose parts of
references allegedly corresponding to the elements recited
in claims 1 and 12, while excluding other parts necessary to
the full appreciation of what such references fairly suggest
to one of ordinary skill in the art, the Patent Office has
relied upon impermissible hindsight, especially in light of
the fact that this patent application was filed nearly 16
years ago. It is respectfully submitted that at the time of
filing this patent application, there is no motivation,
other than impermissible hindsight, for one of ordinary
skill in the art to arrive at the claimed invention.
Patent owner apparently argues that the teaching of using an
SBE mode (page mode) to increase bus bandwidth would not have
been motivation for the combination because the SC2* end-of-cycle
(EOC) signal could not be used to end access to DRAM. Yet again,
the issue is obviousness: would one of ordinary skill in the art
had sufficient skill to interface the "Multibus II" signals to
the "82C08" page mode memory controller? Patent owner's
arguments do not address the level of skill in the art. "82C08"
teaches detecting the beginning and end of SBE mode (page mode)
access using the status lines. The SC2* line in "Multibus II"
indicates a non-final transfer when deasserted (inactive) and an
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