Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
and the replying agent, as evidenced by "iSBC MEM/3XX."** Thus,
the motivation derives from the need to select a memory and
memory controller to implement the memory replying agent.
Second, one skilled in the art would have been motivated, in
particular, to use the "82C08" and its SBE transfer mode,
corresponding to a "page mode," for the memory controller because
the SBE transfer mode has the known advantage that "it performs
high block data transfer which increases the bus bandwidth by
about three times" ("82C08," page 3-4). The '645 patent uses
page mode DRAMs for the same reason (col. 7, lines 63-66): "it
can be appreciated that the page mode type of memory access,
which is a feature of the invention, advantageously provides for
a high bus bandwidth." The page mode of operation was manifestly
designed to be used to increase the data transfer rate and one
skilled in the art would have been motivated to use a page mode
DRAM and a page mode DRAM memory controller for this advantage.
The motivation is based on using a known device for its known
purpose and advantages.
Third, one of ordinary skill in the art seeking to implement
the "Multibus II" sequential transfer protocol would have been
motivated to use the "82C08" memory controller, in particular,
because the "82C08" has structure that supports features of the
Multibus II standard. "Multibus II" indicates initiation of a
sequential transfer when the SC2* signal is not asserted by the
requesting agent during the first reply phase, and indicates the
"end-of-cycle (EOC)" when SC2* is asserted by the requesting
agent during the final reply phase (sheet 2-48). "82C08" has an
"SBE Mode Decoding" block which detects an SBE transfer mode (a
request to initiate a page mode access) when status lines are
active and detects the termination of page mode when the status
lines are inactive (pages 3-15 to 3-16); thus, "82C08" has
structure "for detecting a request for beginning an access to a
memory" and "for detecting a completion of the access to the
memory ... responsive to an end of access control signal," as
claimed. "Multibus II" discloses that "[t]he replying agent must
increment the initial address given by the requesting agent to
obtain the address for subsequent accesses of data when
performing a transfer cycle that requires sequential accesses of
memory" (sheet 2-58). "82C08" discloses that it latches the
initial address and has an "internal counter which supplies the
column address during SBE cycle" (page 3-15); thus, "82C08" has
structure to automatically increment the column addresses
(although this is not claimed). The added motivation is the
support for the Multibus II standard.
Fourth, both "Multibus II" and "82C08" are Intel Corp.
references and one skilled in the art seeking to implement a
"Multibus II" memory replying agent would have been motivated to
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