Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
the cache subsystem may function improperly due to differing
access speeds.
* It is also argued that the Hoffman declaration states (Br42):
* One of ordinary skill in the art around the 1987 time frame
would have realized that one advantage to using such a cache
would be that a large amount of relatively slow and inexpensive
DRAM could be used on the memory board without impacting
performance. Such a person of skill in the art would have also
realized that choice by the memory board manufacturer of using a
cache implied that adding faster DRAM or page mode DRAM would
have had little or no effect on performance and would likely have
required the use of more expensive
**d the rejection does not recognize or address these
difficulties.
-->> is this really challenged?? -->> what is argued?
A person of ordinary skill in the art would have been enabled to
design a memory controller to perform page mode operation. The
'645 patent acknowledges that page mode DRAMs were well known
(col. 6, lines 3-19) and, since the '645 patent provides no
details of the memory controller circuitry, enablement of a page
mode memory controller must be presumed to be within the level
of skill in the art or the '645 patent would not be enabled.
First, "Multibus II" does not describe how a memory and memory
controller for the replying agent are constructed; therefore, one
of ordinary skill seeking to design a memory replying agent would
have motivated to use any commercial type of memory, such as the
"51C64H" DRAM, and any commercial type of memory controller, such
as the "82C08." The motivation derives from the simple fact that
some kind of memory is required. "Multibus II" describes a bus
protocol for conducting memory transfer operations, but leaves it
to designers of ordinary skill in the art to design the
requesting agent and replying agent hardware to implement the
protocol. Those of ordinary skill in the art of computer system
architecture had sufficient knowledge and skill to implement the
Multibus II requesting agent and the replying agent, as evidenced
by "iSBC MEM/3XX."
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