Appeal No. 96-0511
Application 08/158,837
the claimed "plurality of memory cells" and the claimed
"plurality of preliminary memory cells" onto Tanigawa's
memories 10a and 10b, respectively. Appellant does not
contend that Tanigawa fails to satisfy these limitations. The
examiner reads the claimed "means for writing predetermined
external data for functional testing of said plurality of
memory cells into each single row of said plurality of
preliminary memory cells" onto Tanigawa's data write control
circuit (Fig. 1C), which appears to be reasonable to us,
because it writes test data into a pair of elements in a row
of preliminary memory elements (10a) and the language "writing
. . . into each single row of said plurality of preliminary
memory cells" does not require writing into more than one row
of preliminary elements or writing into every memory cell in a
row of preliminary elements. Regarding the claimed "means for
temporarily storing said external data written by said writing
means," the examiner argues (Answer at 3-4 and 9) that such
storing means is inherent in Tanigawa because of his
disclosure that the output data from data output buffer 36 is
applied to an output terminal 38 of the chip and "is sent out
from the chip as an output signal D for comparison with the
out
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