Appeal No. 96-0511
Application 08/158,837
preliminary memory cells in both preliminary memories 11 and
13). Next, the test data are simultaneously transferred from
the memory cells of one row of preliminary memory 11 to the
memory cells of one row of normal memory 1. At the same time,
data are simultaneously transferred from the memory cells of
in one row of the other preliminary memory (13) to the memory
cells in one row of the other normal memory (2). The test
data stored in the two rows of the normal memories are then
simultaneously read and compared with each other to determine
whether or not there is a defect in one of the rows of either
normal memory.
There are five independent claims before us: claims 23,
24, 32, 52, and 53. Independent claims 23 and 25, which
correspond respectively to the two embodiments described
above, read as follows:
23. A semiconductor memory device comprising:
a plurality of memory cells connected to word lines
and bit lines and arranged in a matrix in the direction
of
rows and the direction of columns;
a plurality of preliminary memory cells connected to
preliminary word lines and said bit lines and arranged
in a matrix in said direction of rows and said
direction of columns;
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