Appeal No. 96-0511
Application 08/158,837
this teaching, the examiner cites Childers, which discloses a
semiconductor memory which is constructed to allow high speed
testing to identify row line faults in one example and column
or sense amplifier faults in another example without requiring
the access of the cells in the array in complex data patterns
(col. 1, lines 57-63). The memory array is divided into four
memory blocks 101, 10b, 10c, and 10d (Fig. 1). Figure 6 shows
circuitry for identifying open circuits in row lines 34 and
shorts between row lines (col. 6, lines 10-53). Figure 7, on
which the examiner relies, shows circuitry for identifying
column or sense amplifier faults. Each of the sense
amplifiers 26 is connectable to its corresponding pair of bit
lines 33 by transistors 75 and 76 (operable by voltage T) and
is also connectable to an adjacent set of bit lines by
transistors 75' and 76' (operable by voltage T'). As a
result, the same sense amplifier can be selectively connected
with either set of bit lines to aid in isolating a column
fault (col. 6, line 54 to col. 7, line 16). Another mode of
test operation using the Figure 7 circuitry is to write a data
pattern into the first row in the array, then repeat this
pattern in all 512 other rows without using a complete writing
- 12 -
Page: Previous 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Next
Last modified: November 3, 2007